As is well known, non-volatile memory devices include two basic control terminals which receive a first enable signal, conventionally designated CE and a second enable signal, designated OE. In particular, the first signal CE enables the memory device operation, while the second signal OE enables its communication to internal or external circuitry.
The enable signals, CE and OE, are utilized, for example, to control output lines of memory devices through output buffers which are in a "tri-state" condition, that is a high impedance condition, regulated by the signal OE. In particular, the enable signals CE and OE are applied to such output buffers by specially provided control circuits.
As the enable signal OE assumes a low logic level, or 0 level, the control circuit drives the output buffer to the high impedance condition, thereby enabling the communication of external logics to internal circuitry of the memory device. Likewise, as the enable signal OE assumes a high logic level, or 1 level, the control circuit enables the output buffer to transmit to the outside of the memory device data stored in the inside.
The signal CE sets an operation interval of the memory device, for example to read data which is transferred to the output lines only during the checking of programmed data for correctness, in the course of a programming phase. Thus, the signal CE functions as a signal enabling the checking of programmed data.
Shown schematically in FIG. 1 is a control circuit 1' of an output buffer according to the prior art. The control circuit 1' includes first I1' and second I2' input terminals as well as first O1' and second O2' output terminals. In particular, the first input terminal I1' receives the inverse of the first enable signal OE' and the second input terminal I2' receives the inverse of the second enable signal CE'.
The first input terminal I1' is further coupled to a first input terminal I3' of a multiplexer 2' through a first logic gate 3'. Likewise, the second input terminal I2' is coupled to a second input terminal I4' of the multiplexer 2', through a second logic gate 4'.
The multiplexer 2' has a further input terminal I5' receiving a control signal PG'. The multiplexer 2' also has an output terminal O3' which is coupled to both the first O1' and the second O2' output terminals of the control circuit 1', through respective first 5' and second 6' logic circuits.
The multiplexer 2' will choose between the first OE' and the second CE' enable signal according to the condition of operation of the memory device; that is, it will output the first enable signal OE' while reading of the memory device, the second enable signal CE' being only output during the memory device programming phase to enable the checking during the programming phase.
The first logic circuit 5' comprises substantially first IN1' and second IN2' logic inverters connected in series with each other between the output terminal O3' of the multiplexer 2' and the first output terminal O1' of the control circuit 1'.
The second logic circuit 6' similarly comprises a first logic gate PL1' with two inputs and of a third logic inverter IN3', connected in series with each other between the output terminal O3' of the multiplexer 2' and the second output terminal O2' of the control circuit 1'. In addition, said first logic gate PL1' receives a control signal WORD' at an input terminal I6'.
The first O1' and second O2' output terminals of the control circuit 1' supply first OE.sub.-- L' and second OE.sub.-- H' partial enable signals which are advantageously utilized to control the transfer of discrete sets of bits.
However, the enabling of the read data transfer to the output, as provided by either enable signals OE' and CE', has a response time which is shorter than the propagation time required to complete the reading, from the time the memory is activated, which results in a first random switching of the output stages followed by a second reading, now a consistent one with the memory contents. Thus, it would be desirable to have, at a first reading event, the activation of the output buffers delayed such that the switchings of the output signals cannot perturb the real data read-out process with unreliable switchings.
In fact, the sensitiveness to this undesired phenomenon is higher the more parallel the data, hence the need to have a synchronized enabling for the first read cycle so as to avoid penalties in terms of time. Once the first read cycle is synchronized, no further checking is necessary while the enable signal OE' is at the 0 level.
The underlying technical problem of the present invention is to provide a control circuit of an output buffer, in particular for a non-volatile memory device, which has such structural and functional features as to allow the delaying of just the first switching of the memory device output lines at the end of a true reading interval, thereby overcoming the drawbacks of prior art devices.